The present invention relates to integrated logic circuits, and particularly to logic circuits which include one or more inverter stages.
Power-down of static logic circuits is highly desirable in many applications, both for circuit reasons (average power per chip over a one-second window) and for system reasons (e.g., where a compact battery operated system is to be configured). However, prior art configurations of static logic circuits with power-down capability are not satisfactory. Presently, the power-down of a typical static circuit is implemented using the conventional three transistor inverter stack, as shown in FIG. 1a, as the basic circuit block. It is evident in FIG. 1a showing the conventional power-down inverter stack that this circuit has a unique output. This is so even though there are two different circuit nodes, as in the proposed configuration, because electrically they are always connected through a low impedance depletion type device.
The prior art circuit configuration shown in FIG. 1a has two important problems. First, when the power-up signal and the input signal are both low, the output node is floating. This means that, in a buffer circuit configured using such inverters, such as that shown in FIG. 2a, additional circuitry is required to prevent problems caused by this floating node. For example, in the circuit of FIG. 2a, the additional complementary input marked PU-bar and transistors MX1 and MX2, are required to eliminate deleterious effects of this floating node in the low-input power-down state.
Second, an additional difficulty of the prior art configuration is that a threshold voltage drop from the high rail exists during the on state. That is, when the IN signal is low, the OUT signal will not go all the way up to VCC, but will be less than VDD by 1 threshold voltage.
A further prior art power-down inverter circuit is as shown in FIG. 1c. In this case, the power-up transistor is connected directly to ground, the depletion-load transistor is connected to the power supply, and the third transistor controlled by the input signal is interposed between these other two transistors. This configuration is shown in FIG. 2A of U.S. Pat. No. 4,096,584, which is hereby incorporated by reference. It should be noted that both the power-up and input transistors are enhancement-mode transistors. This means that it may be difficult to pull the output all the way to ground, because of voltage drop across these transistors. This configuration has primarily been used as a NAND of two inputs and not as the power down circuit. Although a NAND configuration is not a novelty in itself, it has never been used for the purpose of saving the power in stand-by mode.
Thus it is an object of the present invention to provide a static power-down inverter which can pull its output node all the way up to supply voltage.
It is a further object of the present invention to provide a static power-down inverter which can pull its output node all the way up to supply voltage or down to within 0.2 volt of ground.
It is a further object of the present invention to provide a power-down buffer which requires only a single power-up signal, and does not require complementary power-up signals nor additional transistors to generate a complement to the power-up signal.
It is a further object of the present invention to provide a power-down buffer requiring only nine active devices, which provides true and complemented outputs but requires only an uncomplemented power-up signal and an uncomplemented input signal.
It is a further object of the invention to provide a power-down buffer requiring only nine active devices, which provides actively driven outputs even in a power-down condition.
According to the present invention, there is provided:
An inverter comprising:
first, second, and third field effect transistors connected in series; PA1 said second source/drain terminal of said first transistor providing a first output node of said circuit; and PA1 said second source/drain terminal of said second transistor providing a second output node of said circuit. PA1 a first field-effect transistor, consisting of a depletion-load transistor, connected between said power supply and a first output node; PA1 second and third field-effect transistors, said second and third transistors being connected in series between said first output node and ground, said second transistor comprising a gate controlled by an input signal and said third transistor comprising a gate controlled by a power-up signal; PA1 wherein at least one of said second and third transistors has a threshold voltage in the range from 0 to 0.4 volts. PA1 first, second, and third inverters, each inverter comprising: PA1 said second source/drain terminal of said first transistor providing a first output node of said circuit; and PA1 said second source/drain terminal of said second transistor providing a second output node of said circuit; PA1 said first inverter being connected to receive an external input, said gate of said third transistor of said second inverter being connected to said first output node of said first inverter, and said gate of said third transistor of said third inverter being connected to said first output node of said second inverter; PA1 said second output node of said second inverter and said second output node of said third inverter being connected to provide complementary buffer output signals. PA1 first, second, and third inverters, each inverter comprising: PA1 wherein at least one of said second and third transistors has a threshold voltage in the range from 0 to 0.4 volts.
said first transistor having a first source/drain terminal connected to a power supply, and also a second source/drain terminal and a gate connected together; PA2 said second transistor having a first source/drain terminal connected to said second source/drain terminal of said first transistor, and also having a seond source/drain terminal, and also having a gate connected to receive a power-up signal; PA2 said third transistor having a first source/drain terminal connected to said second source/drain terminal of said second transistor, and also having a second source/drain terminal connected to a second supply voltage, and also having a gate connected to receive an input signal; PA2 first, second, and third field effect transistors connected in series; said first transistor having a first source/drain terminal connected to a power supply and a second source/drain terminal connected to a gate thereof; PA2 said second transistor having a first source/drain terminal connected to said second source/drain terminal of said first transistor, and also having a second source/drain terminal, and also having a gate connected to receive a power-up signal; PA2 said third transistor having a first source/drain terminal connected to said second source/drain terminal of said second transistor, and also having a second source/drain terminal connected to a second supply voltage, and also having a gate connected to receive an input signal; PA2 a first field-effect transistor, consisting of a depletion-load transistor, connected between said power supply and a first output node; PA2 second and third field-effect transistors, said second and third transistors being connected in series between said first output node and ground, said second transistor comprising a gate controlled by an input signal and said third transistor comprising a gate controlled by a power-up signal;
According to the present invention there is provided:
An inverter comprising:
According to the present invention there is provided:
A buffer circuit comprising:
According to the present invention, there is provided:
A buffer circuit comprising: